Fabrication of vertical fin transistor with multiple threshold voltages

ABSTRACT

A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.

BACKGROUND Technical Field

The present invention relates to vertical fin field effect transistors(finFETs) with graded compound semiconductors, and more particularly toa pair of vertical finFETs having fin channels with different fin widthsand semiconductor compositions.

Description of the Related Art

A Field Effect Transistor (FET) typically has a source, a channel, and adrain, where current flows from the source to the drain, and a gate thatcontrols the flow of current through the channel. Field EffectTransistors (FETs) can have a variety of different structures, forexample, FETs have been formed with the source, channel, and drainformed in the substrate material itself, where the current flowshorizontally (i.e., in the plane of the substrate), and finFETs havebeen formed with the channel extending outward from the substrate, butwhere the current also flows horizontally. The channel for the finFETcan be an upright slab of thin rectangular Si, commonly referred to asthe fin with a gate on the fin, as compared to a MOSFET with a singleplanar gate. Depending on the doping of the source and drain, an n-FETor a p-FET may be formed.

Examples of FETs can include a metal-oxide-semiconductor field effecttransistor (MOSFET) and an insulated-gate field-effect transistor(IGFET). Two FETs also may be coupled to form a complementary metaloxide semiconductor (CMOS), where a p-channel MOSFET and n-channelMOSFET are connected together.

With ever decreasing device dimensions, forming the individualcomponents and electrical contacts becomes more difficult. An approachis therefore needed that retains the positive aspects of traditional FETstructures, while overcoming the scaling issues created by formingsmaller device components.

SUMMARY

A vertical fin field effect transistor including a doped region in asubstrate, wherein the doped region has the same crystal orientation asthe substrate, a first portion of a vertical fin on the doped region,wherein the first portion of the vertical fin has the same crystalorientation as the substrate and a first portion width, a second portionof the vertical fin on the first portion of the vertical fin, whereinthe second portion of the vertical fin has the same crystal orientationas the first portion of the vertical fin, and the second portion of thevertical fin has a second portion width less than the first portionwidth, a gate structure on the second portion of the vertical fin, and asource/drain region on the top of the second portion of the verticalfin.

A pair of vertical fin field effect transistors including a first dopedregion in a substrate, and a second doped region in the substrateadjacent to the first doped region, wherein the first doped region andsecond doped region have the same crystal orientation as the substrate,an unmodified vertical fin on the first doped region, wherein theunmodified vertical fin has the same crystal orientation as thesubstrate and an unmodified width, a modified vertical fin on the seconddoped region, wherein the modified vertical fin has the same crystalorientation as the substrate and at least a portion of the modifiedvertical fin has a modified width less than the unmodified width, a gatestructure on the modified vertical fin, and a gate structure on theunmodified vertical fin.

A method of fabricating one or more vertical fin field effecttransistors including epitaxially growing a first vertical fin ofsilicon-germanium on a substrate, forming a cap on the top surface ofthe first vertical fin, oxidizing the sidewalls of the first verticalfin to form silicon oxide layers at least on opposite sides of the firstvertical fin, and increasing the germanium concentration of the firstvertical fin, and removing the silicon oxide layers to form a portion ofthe first vertical fin having a reduced width.

These and other features and advantages will become apparent from thefollowing detailed description of illustrative embodiments thereof,which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The disclosure will provide details in the following description ofpreferred embodiments with reference to the following figures wherein:

FIG. 1 is a cross-sectional view of a substrate in accordance with anexemplary embodiment;

FIG. 2 is a cross-sectional view of a substrate and isolation region inaccordance with an exemplary embodiment;

FIG. 3 is a cross-sectional view of a substrate with vertical fins inaccordance with an exemplary embodiment;

FIG. 4 is a cross-sectional view of a substrate with a capped verticalfin in accordance with an exemplary embodiment;

FIG. 5 is a cross-sectional view of a capped vertical fin and anoxidized vertical fin in accordance with an exemplary embodiment;

FIG. 6 is a cross-sectional view of a decapped vertical fin and anoxidized vertical fin in accordance with an exemplary embodiment;

FIG. 7 is a cross-sectional view of an unmodified vertical fin and amodified vertical fin in accordance with an exemplary embodiment;

FIG. 8 is a cross-sectional view of a gated unmodified vertical fin anda gated modified vertical fin in accordance with an exemplaryembodiment;

FIG. 9 is a cross-sectional view of a gated unmodified vertical fin anda gated modified vertical fin in accordance with an exemplaryembodiment;

FIG. 10 is a cross-sectional view of a modified and unmodified verticalfin with source regions in accordance with an exemplary embodiment;

FIG. 11 is a cross-sectional view of a pair of vertical finFETs inaccordance with an exemplary embodiment;

FIG. 12 is a cross-sectional view of a substrate in accordance with anexemplary embodiment;

FIG. 13 is a cross-sectional view of a substrate and isolation region inaccordance with an exemplary embodiment;

FIG. 14 is a cross-sectional view of a substrate, isolation region, andhardmask layer in accordance with an exemplary embodiment;

FIG. 15 is a cross-sectional view of a substrate, isolation region, andpatterned hardmask layer in accordance with an exemplary embodiment;

FIG. 16 is a cross-sectional view of a substrate and compoundsemiconductor formed in a patterned hardmask layer in accordance with anexemplary embodiment;

FIG. 17 is a cross-sectional view of a substrate and compoundsemiconductor formed in a patterned hardmask layer with a protectivelayer in accordance with an exemplary embodiment;

FIG. 18 is a cross-sectional view of a substrate and compoundsemiconductor formed in a patterned hardmask layer with a patternedprotective layer in accordance with an exemplary embodiment;

FIG. 19 is a cross-sectional view of a substrate with an oxidizedportion of a compound semiconductor and a protected portion of acompound semiconductor in accordance with an exemplary embodiment;

FIG. 20 is a cross-sectional view of a substrate with a graded compoundsemiconductor and an unmodified compound semiconductor in accordancewith an exemplary embodiment;

FIG. 21 is a cross-sectional view of a substrate with an unmodified finand a modified fin with a vertically graded composition in accordancewith an exemplary embodiment;

FIG. 22 is a cross-sectional view of a substrate with a gated unmodifiedfin and a gated fin with a vertically graded composition in accordancewith an exemplary embodiment; and

FIG. 23 is a cross-sectional view of a vertical fin field effecttransistor.

DETAILED DESCRIPTION

Principles and embodiments of the present disclosure relate generally tovertical finFETs including vertical fins having modified concentrationsof compound semiconductors, and approaches to fabricating vertical finswith modified or graded concentrations of compound semiconductors. Twovertical fins having different widths and different concentrations ofsemiconductor components may be formed adjacent to each other, where theconcentrations of semiconductor components may be modified by selectiveoxidation. The modified concentrations of semiconductor components mayprovide multiple threshold voltages, V_(t), to tune the power andperformance characteristics of the finFET device(s).

One or more embodiments relate to a channel last replacement metal gatevertical finFET having multiple threshold voltages. Multiple thresholdvoltages may be achieved by forming channel regions having differentdopant concentrations. A vertical finFET having multiple thresholdvoltages may be fabricated from silicon-germanium (SiGe) by epitaxiallygrowing one or more SiGe fins from a silicon substrate. An exposedportion of a SiGe fin may be selectively oxidized to increase theconcentration of Ge in the SiGe fin.

In various embodiments, two vertical SiGe fins may be epitaxially grownfrom a silicon substrate, and one of the two vertical SiGe finsselectively oxidized to reduce the width of the vertical fin whileincreasing the concentration of the germanium component in the SiGe fin.

Principle and embodiments of the present disclosure also relate to asemiconductor device structure with conductive elements stacked on thesubstrate to form a conductive path normal to the surface of thesubstrate on which the semiconductor structure is formed. An embodimentrelates generally to a vertical finFET structure that provides multiplethreshold voltages. In an embodiment, a finFET semiconductor device hasthe drain, fin channel, and source device components arrangedperpendicular to the plane of the substrate surface, which is referredto as a vertical stack. A vertically stacked finFET can have a longergate length (i.e., height) and larger dielectric spacer than ahorizontal (i.e., having the drain, fin channel, and source devicecomponents arranged parallel with the plane of the substrate surface)finFET having comparable contact gate pitch.

It is to be understood that the present invention will be described interms of a given illustrative architecture; however, otherarchitectures, structures, substrate materials and process features andsteps may be varied within the scope of the present invention.

It will also be understood that when an element such as a layer, regionor substrate is referred to as being “on” or “over” another element, itcan be directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” or “directly over” another element, there are no interveningelements present. It will also be understood that when an element isreferred to as being “connected” or “coupled” to another element, it canbe directly connected or coupled to the other element or interveningelements may be present. In contrast, when an element is referred to asbeing “directly connected” or “directly coupled” to another element,there are no intervening elements present.

The present embodiments may include a design for an integrated circuitchip, which may be created in a graphical computer programming language,and stored in a computer storage medium (such as a disk, tape, physicalhard drive, or virtual hard drive such as in a storage access network).If the designer does not fabricate chips or the photolithographic masksused to fabricate chips, the designer may transmit the resulting designby physical means (e.g., by providing a copy of the storage mediumstoring the design) or electronically (e.g., through the Internet) tosuch entities, directly or indirectly. The stored design is thenconverted into the appropriate format (e.g., GDSII) for the fabricationof photolithographic masks, which typically include multiple copies ofthe chip design in question that are to be formed on a wafer. Thephotolithographic masks are utilized to define areas of the wafer(and/or the layers thereon) to be etched or otherwise processed.

Methods as described herein may be used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

Reference in the specification to “one embodiment” or “an embodiment” ofthe present principles, as well as other variations thereof, means thata particular feature, structure, characteristic, and so forth describedin connection with the embodiment is included in at least one embodimentof the present principles. Thus, the appearances of the phrase “in oneembodiment” or “in an embodiment”, as well any other variations,appearing in various places throughout the specification are notnecessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”,“and/or”, and “at least one of”, for example, in the cases of “A/B”, “Aand/or B” and “at least one of A and B”, is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of both options (A andB). As a further example, in the cases of “A, B, and/or C” and “at leastone of A, B, and C”, such phrasing is intended to encompass theselection of the first listed option (A) only, or the selection of thesecond listed option (B) only, or the selection of the third listedoption (C) only, or the selection of the first and the second listedoptions (A and B) only, or the selection of the first and third listedoptions (A and C) only, or the selection of the second and third listedoptions (B and C) only, or the selection of all three options (A and Band C). This may be extended, as readily apparent by one of ordinaryskill in this and related arts, for as many items listed.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises,” “comprising,” “includes” and/or “including,” when usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper,” and the like, may be used herein for ease of description todescribe one element's or feature's relationship to another element(s)or feature(s) as illustrated in the FIGs. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the FIGs. For example, if the device in theFIGs. is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device may be otherwise oriented (rotated 90degrees or at other orientations), and the spatially relativedescriptors used herein may be interpreted accordingly. In addition, itwill also be understood that when a layer is referred to as being“between” two layers, it can be the only layer between the two layers,or one or more intervening layers may also be present.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another element. Thus, a first element discussed belowcould be termed a second element without departing from the scope of thepresent concept.

In various embodiments, the materials and layers may be deposited byphysical vapor deposition (PVD), chemical vapor deposition (CVD), atomiclayer deposition (ALD), molecular beam epitaxy (MBE), or any of thevarious modifications thereof, for example plasma-enhanced chemicalvapor deposition (PECVD), metal-organic chemical vapor deposition(MOCVD), low pressure chemical vapor deposition (LPCVD), electron-beamphysical vapor deposition (EB-PVD), and plasma-enhanced atomic layerdeposition (PE-ALD). The depositions may be epitaxial processes, and thedeposited material may be crystalline. In various embodiments, formationof a layer may be by one or more deposition processes, where, forexample, a conformal layer may be formed by a first process (e.g., ALD,PE-ALD, etc.) and a fill may be formed by a second process (e.g., CVD,electrodeposition, PVD, etc.).

Referring now to the drawings in which like numerals represent the sameor similar elements and initially to FIG. 1, which is a cross-sectionalview of a substrate in accordance with an exemplary embodiment.

In one or more embodiments, a vertical fin may be formed on acrystalline substrate, where the substrate may have a surface with alattice constant that facilitates epitaxial growth of a compoundsemiconductor. In various embodiments, the substrate 110 may be asemiconductor substrate, where the substrate may be a single crystalsemiconductor wafer or a crystalline semiconductor layer on a supportingwafer. In various embodiments, the substrate may be silicon orsilicon-germanium. The substrate may be a semiconductor-on-insulator(SeOI), silicon-on-insulator (SOI), or silicon-germanium-on-insulator(SGOI). The substrate 110 may have a <100> or a <111> crystal faceexposed for subsequent depositions, where the crystal lattice mayfacilitate epitaxial growth.

FIG. 2 is a cross-sectional view of a substrate and isolation region inaccordance with an exemplary embodiment.

In one or more embodiments, a substrate may be masked and patterned toform one or more trench(es) in which an insulator material may beformed. The trench and insulator material may provide an isolationregion 120 for subsequent layers and structures formed on the substrate.In various embodiments, the isolation region 120 provides shallow trenchisolation for adjacent device structures, where the device structuresmay be vertical finFETs. In one or more embodiments, the isolationregion 120 includes an oxide, for example, silicon oxide (SiO_(x)).

FIG. 3 is a cross-sectional view of a substrate with vertical fins inaccordance with an exemplary embodiment.

In one or more embodiments, a hardmask may be formed on the substrate110, patterned, and etched to expose a portion of the substrate 110. Avertical fin 140 may be formed on at least the exposed portions of thesubstrate 110, where the vertical fin 140 may be formed by any knownpatterning techniques, for example, sidewall image transfer, lithographyand etching, and epitaxy. In various embodiments, the vertical fin 140may be epitaxially grown from the crystalline surface of the substrate.

In various embodiments, the vertical fin 140 may be a compoundsemiconductor, for example, silicon-germanium (SiGe). In variousembodiments, the crystal lattice of the exposed substrate surface may beselected to control the amount of stress induced in the epitaxiallygrown compound semiconductor material. In various embodiments, thesubstrate 110 may be silicon, and the vertical fin 140 may be SiGe. TheSiGe fin may be formed by first epitaxially growing a SiGe layer on thesurface of the Si substrate. A suitable patterning technique may then beapplied to pattern the epitaxially grown SiGe layer into one or morevertical fin(s) 140. In some embodiments, the substrate surface may bemasked and patterned to provide exposed portions of the substrate onwhich vertical fin(s) 140 may be epitaxially grown. The mask may then beremoved to expose the substrate surface between the vertical fin(s) 140.

In one or more embodiments, the exposed portion of the substrate in themask pattern may have a width in the range of about 5 nm to about 25 nm,or in the range of about 10 nm to about 20 nm, or in the range of about10 nm to about 15 nm. In various embodiments, the vertical fin 140 mayhave a width in the range of about 5 nm to about 25 nm, or in the rangeof about 10 nm to about 20 nm, or in the range of about 10 nm to about15 nm.

In various embodiments, a bottom spacer 130 may be formed on theportions of the substrate 110, where the bottom spacer 130 may bebetween at least a doped region (e.g., source/drain) and a subsequentlyformed gate structure. The bottom spacer 130 may provide electricalinsulation between the substrate 110 and/or doped region (e.g.,source/drain) and a gate structure formed on the vertical fin 140. Theheight (i.e., thickness) of the bottom spacer 130 may be less than theheight of the fin 140. In various embodiments, the bottom spacer 130 maybe a nitride, for example, silicon nitride (SiN). The vertical fin(s)140 may have a cap 150 formed on the top surface to protect the fin 140during various processing steps of device manufacturing.

FIG. 4 is a cross-sectional view of a substrate with a capped verticalfin in accordance with an exemplary embodiment.

In one or more embodiments, a protective cap 160 may be formed over oneor more vertical fin(s), where the protective cap 160 may be formedconformally over the sidewalls of the vertical fin 140. In variousembodiments, the protective cap 160 may be deposited by atomic layerdeposition (ALD) or chemical vapor deposition (CVD), a variation thereof(e.g., plasma enhanced, low pressure, metal-organic, etc.), and/or acombination thereof. One or more vertical fin(s) 140 may not be coveredby a protective cap 160, such that the sidewalls of the unprotectedvertical fin(s) 140 remain exposed.

In various embodiments, the protective cap 160 may be a nitride, forexample, silicon nitride (SiN).

FIG. 5 is a cross-sectional view of a capped vertical fin and anoxidized vertical fin in accordance with an exemplary embodiment.

In one or more embodiments, the bottom spacer 130, protective cap 160,and exposed vertical fin 140 may be exposed to an oxidizing environment,for example, dry thermal oxidation in an oxygen atmosphere or use of anoxygen plasma. In various embodiments, the oxidizing conditions maydepend on the oxidation target. The oxidation may be performed in anoxygen environment at a temperature in the range of about 800° C. toabout 1100° C. for a time period in the range of about 10 seconds toabout 1 hour, or about 1 minute to about 30 minutes. In variousembodiments, the silicon of the SiGe of the exposed fin 140 may beselectively oxidized to increase the ratio of germanium to silicon inthe remaining SiGe.

The oxidation of exposed SiGe may produce germanium enrichment in theexposed vertical fin 140. A modified vertical fin 180, having a higherGe concentration in at least a portion of the vertical fin, may beformed from the unmodified vertical fin 140. The oxidation of the Si mayalso reduce the width of at least a portion of the vertical fin 140 asthe silicon is converted to silicon oxide (e.g., SiO₂) to form anarrower modified vertical fin 180, and silicon oxide layer(s) 170. Invarious embodiments, vertical fin(s) 140 to be modified may initially beformed with a greater width than vertical fin(s) 140 that remainsunmodified. In this manner, vertical FET channels having the same widthmay be obtained by starting with wider vertical fin 140 for the SiGefins intended to have greater Ge concentration to accommodate theconsumption of the Si in the SiGe through the condensation oxidation.

In various embodiments, the modified vertical fin 180 may have a firstportion 145, which may be below the level of the bottom spacer 130, anda second portion 181 above the level of the bottom spacer 130, where thesecond portion 181 has a narrower width and a higher Ge concentration.The first portion 145 of the modified vertical fin 180 may be on thesubstrate and the second portion of the modified vertical fin 180 may beon the first portion 145, which remains essentially unmodified. Thefirst portion 145 of the vertical fin 180 may have the same crystalorientation as the substrate 110 and a first portion width, and a secondportion 181 of the vertical fin 180 may have the same crystalorientation as the first portion 145 of the vertical fin, and the secondportion 181 of the vertical fin may have a second portion width lessthan the first portion width.

In an exemplary embodiment, two vertical fins 140 of SiGe, referred toas a first vertical fin and a second vertical fin, may be epitaxiallygrown on a single crystal silicon substrate 110. The first vertical fin140 may be covered with a protective cap 160, and the exposed sidewallsof the second vertical fin 140 may be oxidized to a depth less than thewidth of the second vertical fin 140, where oxidation of the SiGeselectively consumes silicon to form a silicon oxide layer 170, andredistributes the germanium at the oxidation interface. Since a portionof the second vertical fin remains covered by the bottom spacer 130during oxidation, a first portion 145 of the second vertical fin 140 mayremain unmodified. The second portion 181 of the modified vertical fin180 may have a greater percentage of germanium than the first portion145 of the vertical fin. The first portion 145 of the vertical fin 180may have the same crystal orientation as the substrate 110, and thesecond portion 181 of the vertical fin 180 may have the same crystalorientation as the first portion 145 of the vertical fin.

In various embodiments, an unmodified vertical fin 140 may have agermanium concentration in the range of about 10 at. % Ge to about 40at. % Ge, or in the range of 20 at. % Ge to about 30 at. % Ge. Invarious embodiments, at least a second portion 181 of a modifiedvertical fin 180 may have a germanium concentration in the range ofabout 20 at. % Ge to about 50 at. % Ge, or in the range of 30 at. % Geto about 50 at. % Ge, or in the range of about 20 at. % Ge to about 40at. % Ge, although a greater or lesser germanium concentration is alsoconsidered within the scope of the disclosure.

In various embodiments, the modified vertical fin 180 has a lowerthreshold voltage, V_(t), than the unmodified vertical fin 140 due tothe increased Ge concentration in at least the second portion 181. Whilenot being bound by theory, the threshold voltage may be reduced byincreasing the Ge concentration due to a narrowing of the band gap ofthe SiGe and/or a strain change in the SiGe material.

In various embodiments, at least a second portion 181 of the modifiedvertical fin 180 may have a width in the range of about 5 nm to about 20nm, or in the range of about 7 nm to about 18 nm, or in the range ofabout 7 nm to about 12 nm. The unmodified vertical fin portion 145 mayretain the initial width and concentration ratio of Si to Ge, which maybe essentially the same as vertical fin 140.

FIG. 6 is a cross-sectional view of a decapped vertical fin and anoxidized vertical fin in accordance with an exemplary embodiment.

In one or more embodiments, the protective cap 160 and cap 150 may beremoved to expose the unmodified vertical fin 140 and top surface of themodified vertical fin 180. The protective cap 160 and cap 150 may beselectively removed by suitable etching. The silicon oxide layers 170may remain on the sidewalls of the second portion 181 of the modifiedvertical fin 180, and cover at least the first portion 145 of thevertical fin that remained unmodified. The silicon oxide layers may beformed at least on opposite sides of the vertical fin, and may surroundthe vertical fin.

FIG. 7 is a cross-sectional view of an unmodified vertical fin and amodified vertical fin in accordance with an exemplary embodiment.

In one or more embodiments, the silicon oxide layer(s) 170 may beremoved from the sidewalls of the modified vertical fin 180 to exposethe sidewalls of the modified vertical fin 180. The silicon oxidelayer(s) 170 may be selectively removed by suitable etching.

FIG. 8 is a cross-sectional view of a gated unmodified vertical fin anda gated modified vertical fin in accordance with an exemplaryembodiment.

In one or more embodiments, a gate structure 190 may be formed on thesidewalls of unmodified vertical fin 140 and/or modified vertical fin180, where the gate structure 190 may include a conductive gate and aninsulating layer between a vertical fin and the conductive gate.Formation of the gate structure 190 may be accomplished by suitablemasking, patterning, and/or depositions.

In one or more embodiments, the conductive gate and an insulating layerform the gate structure 190 with the vertical fin 140, 180 for controlof current through the vertical fin 140, 180, where the gate structure190 may be on the sidewalls and surround the vertical fin 140, 180. Invarious embodiments, the gate structure may have a height in the rangeof about 10 nm to about 300 nm, or about 15 nm to about 200 nm, or about20 nm to about 100 nm.

In one or more embodiments, each gate structure includes a gatedielectric layer and a gate conductor layer. The gate dielectric layermay have a thickness in the range of about 1 nm to about 5 nm. Invarious embodiments, the insulating layer formed on the modifiedvertical fin 180 may have the same thickness as the insulating layerformed on the unmodified vertical fin 140. The gate dielectric materialmay be a silicon oxide (e.g., SiO2), a silicon nitride (e.g., Si₃N₄),silicon oxynitride (SiON), boron nitride (e.g., BN) a high-K material,or a combination thereof. Examples of high-k materials include but arenot limited to metal oxides such as hafnium oxide (e.g., HfO₂), hafniumsilicon oxide (e.g., HfSiO₄), hafnium silicon oxynitride(Hf_(w)Si_(x)O_(y)N_(z)), lanthanum oxide (e.g., La₂O₃), lanthanumaluminum oxide (e.g., LaAlO₃), zirconium oxide (e.g., ZrO₂), zirconiumsilicon oxide (e.g., ZrSiO₄), zirconium silicon oxynitride(Zr_(w)Si_(x)O_(y)N_(z)), tantalum oxide (e.g., TaO₂, Ta₂O₅), titaniumoxide (e.g., TiO₂), barium strontium titanium oxide (e.g.,BaTiO₃—SrTiO₃), barium titanium oxide (e.g., BaTiO₃), strontium titaniumoxide (e.g., SrTiO₃), yttrium oxide (e.g., Y₂O₃), aluminum oxide (e.g.,Al₂O₃), lead scandium tantalum oxide (Pb(Sc_(x)Ta_(1-x))O₃), and leadzinc niobate (e.g., PbZn_(1/3)Nb_(2/3)O₃). The high-k may furtherinclude dopants such as lanthanum and/or aluminum. The stoichiometry ofthe high-K compounds may vary.

In one or more embodiments, the gate conductor may have a thickness inthe range of about 5 nm to about 50 nm. The gate conductor material maybe polycrystalline or amorphous silicon, germanium, silicon germanium, ametal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt,copper, aluminum, lead, platinum, tin, silver, gold), a conductingmetallic compound material (e.g., tantalum nitride, titanium nitride,tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide,nickel silicide), carbon nanotube, conductive carbon, graphene, or anysuitable combination of these materials. The conductive material mayfurther comprise dopants that are incorporated during or afterdeposition. The stoichiometry of the conductive material compounds mayvary.

FIG. 9 is a cross-sectional view of a gated unmodified vertical fin anda gated modified vertical fin in accordance with an exemplaryembodiment.

In one or more embodiments, a top spacer 200 may be formed on thesidewall(s) of the unmodified vertical fin 140 and/or modified verticalfin 180, where the top spacer may electrically isolate at least theconductive gate of the gate structure 190 from a subsequently formedsource/drain region of a finFET. The spacer may be an oxide, for examplesilicon oxide (SiO), a nitride, for example, silicon nitride (SiN),and/or an oxy-nitride, for example, silicon oxynitride (SiON). The topspacer 200 may be between the gate structure 190 and a source/drainregion on the second portion 181 of the vertical fin 180.

FIG. 10 is a cross-sectional view of a modified and unmodified verticalfin with source/drain regions in accordance with an exemplaryembodiment.

In one or more embodiments, a source/drain region 210 may be formed onthe top surface of the unmodified vertical fin 140 and/or modifiedvertical fin 180, where the source/drain region 210 may be formed byepitaxial growth on the unmodified vertical fin 140 and/or modifiedvertical fin 180. The source/drain region 210 may have the same crystalorientation as the vertical fin on which it is formed. It should benoted that the source and drain can be interchangeable between the topand bottom locations of a vertical fin. The formation may be epitaxialgrowth of a semiconductor material, such as silicon or silicon-germaniumon a germanium-enriched SiGe vertical fin 180. In various embodiments,the epitaxial material may be in-situ doped (i.e., during epitaxy) orex-situ doped (i.e., after epitaxy). Doping may be p-type doping orn-type doping.

FIG. 11 is a cross-sectional view of a pair of vertical finFETs inaccordance with an exemplary embodiment.

In one or more embodiments, a doped region (e.g., source/drain) 220 maybe formed in the substrate 110 below unmodified vertical fin 140 and/ormodified vertical fin 180. The doped region 220 may be formed by anysuitable doping technique, for example, ion implantation, in-situ dopedepitaxy, etc. The doped region 220 may be n-doped or p-doped. Theshallow trench isolation (STI) may be between the location of a firstvertical fin and the location of a second vertical fin. In variousembodiments, two adjacent doped regions 220 may be formed in thesubstrate 110, and referred to as a first doped region (e.g.,source/drain) and a second doped region (e.g., source/drain). Theshallow trench isolation may be situated between the doped regions 220of the unmodified vertical fin 140 and/or modified vertical fin 180 toprovide electrical isolation.

FIG. 12 is a cross-sectional view of a substrate in accordance with anexemplary embodiment.

In one or more embodiments, a substrate 110 may be a semiconductorsubstrate, where the substrate may be a single crystal semiconductorwafer or a crystalline semiconductor layer on a supporting wafer. Invarious embodiments, the substrate may be silicon or silicon-germanium.The substrate may be a semiconductor-on-insulator (SeOI),silicon-on-insulator (SOI), or silicon-germanium-on-insulator (SeGeOI).The substrate 110 may have a <100> or a <111> crystal face exposed forsubsequent depositions, where the crystal lattice may facilitateepitaxial growth.

FIG. 13 is a cross-sectional view of a substrate and isolation region inaccordance with an exemplary embodiment.

In one or more embodiments, a substrate may be masked and patterned toform one or more trench(es) in which an insulator material may beformed. The trench and insulator material may provide an isolationregion 120 for subsequent layers and structures formed on the substrate,where the isolation region 120 may include an oxide, for example,silicon oxide (SiO_(x)) to provide electrical isolation.

FIG. 14 is a cross-sectional view of a substrate, isolation region, andhardmask layer in accordance with an exemplary embodiment.

In one or more embodiments, a hardmask layer 132 may be formed on thesubstrate 110 and isolation region 120. In various embodiments, thehardmask layer 132 may be a nitride, for example, silicon nitride.

FIG. 15 is a cross-sectional view of a substrate, isolation region, andpatterned hardmask layer in accordance with an exemplary embodiment.

In one or more embodiments, the hardmask layer 132 may be masked andpatterned, and trenches 135 formed in the hardmask layer 132, where thetrenches 135 may be formed by reactive ion etching (RIE). The trenches135 may extend to the surface of the substrate, such that the crystallattice of the substrate surface is exposed at the bottom of the trench135.

In various embodiments, the trenches 135 may have a width in the rangeof about 8 nm to about 25 nm, or in the range of about 10 nm to about 20nm, or in the range of about 10 nm to about 15 nm.

FIG. 16 is a cross-sectional view of a substrate and compoundsemiconductor formed in a patterned hardmask layer in accordance with anexemplary embodiment.

In one or more embodiments, a fin material 141 may be formed in thetrenches, where the fin material 141 may extend above the surface of thehardmask layer 132. The in material 141 may be formed in the trenches135 by epitaxial deposition, where the deposition may be heteroepitaxialgrowth of a SiGe vertical fin 140 on a crystalline silicon substratesurface. The fin material 141 may be a doped semiconductor or compoundsemiconductor, for example, SiGe.

FIG. 17 is a cross-sectional view of a substrate and compoundsemiconductor formed in a patterned hardmask layer with a protectivelayer in accordance with an exemplary embodiment.

In one or more embodiments, a cap layer 151 may be formed on the exposedsurface of the fin material 141. The cap layer 151 may be a nitride, forexample, silicon nitride (SiN).

FIG. 18 is a cross-sectional view of a substrate and compoundsemiconductor formed in a patterned hardmask layer with a patternedprotective layer in accordance with an exemplary embodiment.

In one or more embodiments, the cap layer 151 may be masked, patterned,and etched to remove at least a portion of cap layer 151 from one ormore regions above a trench 135 having a fill of fin material 141, whileleaving a capped portion 155 over one or more regions above a trench 135having a fill of fin material 141.

FIG. 19 is a cross-sectional view of a substrate with an oxidizedportion of a compound semiconductor and a protected portion of acompound semiconductor in accordance with an exemplary embodiment.

In one or more embodiments, the exposed fin material 141 may beoxidized, for example, by a dry thermal oxidation, to produce germaniumcondensation in at least a portion of the fill of fin material 141 in atrench 135. A silicon oxide layer 170 may be formed over a graded finmaterial 183, where oxidation of SiGe selectively consumes silicon toform a silicon oxide layer 170, and redistributes the germanium at theoxidation interface. The upper portion 185 of the modified vertical fin180 may have an increased germanium concentration, and a second portion181 of the modified vertical fin 180 may have a vertically gradedgermanium concentration, while a first portion 145 may retain theinitial concentration ratio of Si to Ge, which may be essentially thesame as fin material 141.

FIG. 20 is a cross-sectional view of a substrate with a graded compoundsemiconductor and an unmodified compound semiconductor in accordancewith an exemplary embodiment.

In one or more embodiments, the capped portion 155, exposed fin material141, and top portion of the graded fin material 183 may be removed,where the material layers may be removed by any suitable removalprocess, for example, chemical-mechanical polishing and/or selectiveetching.

FIG. 21 is a cross-sectional view of a substrate with an unmodified finand a modified fin with a vertically graded composition in accordancewith an exemplary embodiment.

In one or more embodiments, the hardmask layer 132 may be removed, and abottom spacer 130 may be formed between the substrate and a portion ofthe modified vertical fin and the unmodified vertical fin. The bottomspacer material 130 may be formed by a suitable deposition process,which may be followed by a suitable etch. The hardmask layer 132 may berecessed to leave a portion of the hardmask along the bottom of thetrench. In various embodiments, a remaining portion of hardmask layer132 may become the bottom spacer 130.

FIG. 22 is a cross-sectional view of a substrate with a gated unmodifiedfin and a gated fin with a vertically graded composition in accordancewith an exemplary embodiment.

In one or more embodiments, a gate structure 190 may be formed on theunmodified fin, and a gate structure may be formed on the modified fin.

In a non-limiting exemplary embodiment, a vertical fin field effecttransistor includes a doped region 220 in a substrate 110, wherein thedoped region 220 has the same crystal orientation as the substrate 110,a first portion 145 of a vertical fin on the doped region, wherein thefirst portion 145 of the vertical fin has the same crystal orientationas the substrate 110 and a first portion width, a second portion 181 ofthe vertical fin on the first portion 145 of the vertical fin, whereinthe second portion 181 of the vertical fin has the same crystalorientation as the first portion 145 of the vertical fin, and the secondportion 181 of the vertical fin has a second portion width less than thefirst portion width, wherein the first portion 145 of the vertical finand the second portion 181 of the vertical fin are silicon germanium,the second portion 181 of the vertical fin has a greater percentage ofgermanium than the first portion 145 of the vertical fin, and the secondportion 181 of the vertical fin has a vertically graded germaniumconcentration, a gate structure 190 on the second portion 181 of thevertical fin, and a source/drain region 210 on the top of the secondportion 181 of the vertical fin.

While the embodiments have been depicted and described with particulararrangements and orientations, this is for descriptive purposes only. Invarious embodiments, for example, the locations of the source and drainof a vertical transistor may be reversed such that the drain is on thetop of a vertical fin, while the source is at the bottom. The sourcemay, therefore, be at the bottom or the top. Similarly, while thefigures have been depicted and described with a modified vertical finadjacent to a non-modified vertical fin, various patterns andarrangements having different sequences of modified and unmodified finsare also contemplated.

Having described preferred embodiments of the fabrication of verticalfin transistors with multiple threshold voltages (which are intended tobe illustrative and not limiting), it is noted that modifications andvariations can be made by persons skilled in the art in light of theabove teachings. It is therefore to be understood that changes may bemade in the particular embodiments disclosed which are within the scopeof the invention as outlined by the appended claims. Having thusdescribed aspects of the invention, with the details and particularityrequired by the patent laws, what is claimed and desired protected byLetters Patent is set forth in the appended claims.

What is claimed is:
 1. A method of fabricating a pair of vertical finfield effect transistors, comprising: epitaxially growing a firstvertical fin of silicon-germanium on a substrate; epitaxially growing asecond vertical fin of silicon-germanium on the substrate; forming a capon the top surface of the first vertical fin; forming a protective capover the top surface and sidewalls of the second vertical fin beforeoxidizing the sidewalls of the first vertical fin, so only the sidewallsof the first vertical fin form silicon oxide layers; oxidizing thesidewalls of the first vertical fin to form silicon oxide layers atleast on opposite sides of the first vertical fin, and increasing thegermanium concentration of the first vertical fin; and removing thesilicon oxide layers to form a portion of the first vertical fin havinga reduced width.
 2. The method of claim 1, wherein the substrate iscrystalline silicon.
 3. The method of claim 1, further comprising,removing the protective cap from the second vertical fin and the capfrom the top surface of the first vertical fin.
 4. The method of claim3, further comprising, forming a bottom spacer on the substrate; forminga first gate structure on the first vertical fin; and forming a secondgate structure on the second vertical fin.
 5. The method of claim 4,further comprising forming shallow trench isolation in the substrate,wherein the shallow trench isolation is between the location of thefirst vertical fin and the location of the second vertical fin.
 6. Themethod of claim 1, wherein the concentration of germanium in at least aportion of the first vertical fin is greater than the concentration ofgermanium in the second vertical fin.
 7. The method of claim 6, whereinat least a portion of the first vertical fin has a vertically gradedgermanium concentration.
 8. The method of claim 6, wherein the firstvertical fin with the reduced width has a germanium concentration in therange of about 20 at. % Ge to about 50 at. % Ge.
 9. The method of claim8, wherein the first vertical fin with the reduced width has a greatergermanium concentration than the second vertical fin.
 10. The method ofclaim 9, wherein the first vertical fin with the reduced width has areduced threshold voltage compared to the second vertical fin.
 11. Amethod of fabricating a pair of vertical fin field effect transistors,comprising: epitaxially growing a first vertical fin ofsilicon-germanium on a single-crystal silicon substrate; epitaxiallygrowing a second vertical fin of silicon-germanium on the single-crystalsilicon substrate; forming a cap on the top surface of the firstvertical fin; forming a protective cap over the top surface andsidewalls of the second vertical fin before oxidizing the sidewalls ofthe first vertical fin, so only the sidewalls of the first vertical finform silicon oxide layers; oxidizing the sidewalls of the first verticalfin to form silicon oxide layers at least on opposite sides of the firstvertical fin, and increasing the germanium concentration of the firstvertical fin; removing the silicon oxide layers to form a portion of thefirst vertical fin having a reduced width; and removing the protectivecap from the second vertical fin and the cap from the top surface of thefirst vertical fin.
 12. The method of claim 11, further comprising,forming a first gate structure on the first vertical fin, and forming asecond gate structure on the second vertical fin.
 13. The method ofclaim 12, wherein the first gate structure on the first vertical fin andthe second gate structure on the second vertical fin each includes agate dielectric layer and a gate conductor layer.
 14. The method ofclaim 13, further comprising, forming a first source/drain region on thefirst vertical fin, and forming a second source/drain region on thesecond vertical fin.
 15. The method of claim 14, further comprising,forming a shallow trench isolation region between the first vertical finand second vertical fin.
 16. A method of fabricating a pair of verticalfin field effect transistors, comprising: forming a shallow trenchisolation region in a single-crystal silicon substrate; forming ahardmask layer on the single-crystal silicon substrate and the shallowtrench isolation region, wherein the shallow trench isolation region isbelow the hardmask layer; forming a first trench in the hardmask layeron one side of the shallow trench isolation region, and a second trenchin the hardmask layer on the opposite side of the shallow trenchisolation region from the first trench; forming a silicon-germanium finmaterial in the first trench and the second trench, wherein thesilicon-germanium fin material extends above a top surface of thehardmask layer; forming a capped portion over the first trench;oxidizing the silicon-germanium fin material to form a silicon oxidelayer, a graded fin material over the second trench, and a modifiedvertical fin having an upper portion with an increased germaniumconcentration in the second trench; removing the capped portion andsilicon oxide layer; and removing the silicon-germanium fin material andgraded fin material.
 17. The method of claim 16, further comprising,removing the hardmask layer to expose an unmodified vertical fin and themodified vertical fin.
 18. The method of claim 17, further comprising,forming a first gate structure on the modified vertical fin, and asecond gate structure on the unmodified vertical fin.
 19. The method ofclaim 18, wherein the modified vertical fin has a second portion with avertically graded germanium concentration.
 20. The method of claim 19,further comprising, forming a first source/drain region on the top ofthe unmodified vertical fin, and a second source/drain region on the topof the modified vertical fin.